In the prior art, the method for forming a semiconductor device comprises: first, as shown in FIG. 1, forming a trench 30 in a semiconductor substrate 10 (a hard mask 20, e.g., silicon oxide may be previously formed on a surface of the semiconductor substrate 10); then, as shown in FIG. 2, filling the trench 30 with an insulating material (e.g., silicon oxide), so as to form isolation regions 32 (e.g., STIs) and an active region 12 surrounded by the isolation regions 32 in the semiconductor substrate 10; and then, as shown in FIG. 3, forming at least one gate stack structure (and source and drain regions 60) and an interlayer dielectric layer 50 (e.g., doped or undoped silicon oxide) located between the gate stack structures (including a gate dielectric layer 44, a gate electrode 40 formed on the gate dielectric layer 44, and spacers 42 surrounding the gate dielectric layer 44 and the gate electrode 40) on the active region 12. After contact holes are formed in the interlayer dielectric layer 50, the semiconductor device may be interconnected through external conductors. In other words, the gate stack structure is formed after formation of the isolation region 32.
For various considerations (e.g., cost), it is always desired in the industry to reduce the area of isolation regions so as to increase the area of the active region, such that the number of the devices formed in a unit area of the semiconductor substrate may be increased. However, various narrow effects begin to emerge with continuous reduction in the critical dimension of the semiconductor device. It becomes more difficult to reduce the area of the isolation regions due to the limitation of design rules for the semiconductor device.